Computer System Modeling and Verification

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Prerequisites:

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Computer Science or Computer/Electrical Engineering Bachelor.

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Pedagogical objectives:

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Students who take this course will gain an understanding of the concepts and theories of computer-aided formal specification and verification, and learn how to use and write formal verification tools.

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Evaluation modalities:

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continuous reporting, final exam

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Description:

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Most of the course is devoted to high-level semantic design and code-level properties. The emphasis is put on executable specifications and verification tools based on the following methods:

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  • Static analysis and type checking
  • Design-by-contract and property-based testing
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Static and dynamic verification in particular are compared in this course, with a focus on tools and prototype development:

  • Preliminaries
    • Imperative programming and unit testing
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    • Functional programming and logic
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  • Part I: static analysis
    • Specification: typing rules (deductive system)
    • Implementation: mode-based extraction of functional code
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  • Part II: dynamic verification
    • Specification: design-by-contract
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    • Implementation: self-testing and property-based testing
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Required teaching material
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Teaching volume:
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lessons:
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28-35 heurs
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Exercices:
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0-5 hours
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Supervised lab:
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0-28 hours
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Devices:

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